TSMC Unveils Advanced A14 Process Amid AI Boom

SANTA CLARA, Calif., At its North America Technology Symposium, Taiwan Semiconductor Manufacturing Co. (TSMC) recently unveiled its next-generation logic process technology, A14. 

The announcement comes as TSMC navigates booming demand for artificial intelligence chips while facing complex geopolitical dynamics and competitive pressures, particularly from its U.S. rival, Intel Corp.

The A14 process represents a significant leap from TSMC’s current N2 technology, which is entering volume production later this year. Designed to power the ongoing AI transformation, the A14 will deliver enhanced computing performance and greater power efficiency. 

Specifically, compared to the N2 process, the A14 could offer up to a 15% speed improvement at the same power level or reduce power consumption by up to 30% at the same speed. 

Furthermore, it promises more than a 20% increase in logic density. TSMC stated the A14 development is proceeding smoothly, with yield performance currently ahead of schedule. The company plans for A14 to enter production in 2028.

Driving AI and HPC

TSMC highlighted that the A14 technology leverages its experience in design-technology co-optimization for nanosheet transistors. This advancement is coupled with the company’s standard cell architecture evolution, moving from TSMC NanoFlex to NanoFlex Pro to offer improved performance, power efficiency, and design flexibility. 

Dr. C.C. Wei, TSMC Chairman and CEO, emphasized that technologies like A14 are part of a broader suite of solutions connecting the physical and digital worlds to “unleash our customers’ innovation for advancing the AI future.”

Beyond the core logic process, TSMC also showcased a range of complementary technologies essential for building the advanced chips required across various sectors. For high-performance computing (HPC), particularly for AI, the company is advancing its Chip on Wafer on Substrate (CoWoS) technology. 

Insatiable need for performance

This technology addresses the “insatiable need for more logic and high-bandwidth memory (HBM)” driven by AI. TSMC plans for a 9.5 reticle size CoWoS to reach volume production in 2027, enabling the integration of 12 or more HBM stacks alongside leading-edge logic. Following its 2024 debut of System-on-Wafer (TSMC-SoW) technology, 

TSMC introduced SoW-X, a CoWoS-based solution aiming to create a wafer-sized system with computing power 40 times that of the current CoWoS offering. It is also slated for volume production in 2027.

Other HPC solutions include silicon photonics integration using TSMC’s Compact Universal Photonic Engine (COUPE), N12 and N3 logic base dies for HBM4 and a new Integrated Voltage Regulator (IVR) for AI that delivers 5 times the vertical power density compared to a separate power management chip on a circuit board.

The company is applying its technological advancements across other key markets. For smartphones, it is supporting AI on edge devices and their need for high-speed, low-latency wireless connectivity with N4C RF technology. 

The latest radio frequency offering provides a 30% reduction in power and area compared to N6RF+. It is suitable for integrating more digital content into RF system-on-chip designs for standards like WiFi 8 and AI-rich True Wireless Stereo. N4C RF would enter risk production in the first quarter of 2026.

In the automotive sector, where advanced driver assistance systems (ADAS) and autonomous vehicles (AV) demand significant computing power alongside stringent quality and reliability, TSMC is deploying its most advanced N3A process. 

The process is undergoing the final stage of AEC-Q100 Grade-1 qualification and continuous defect improvement to meet automotive defective parts per million (DPPM) requirements, and it is now entering production for automotive applications.

For the Internet of Things (IoT), as devices incorporate AI functionality on limited battery budgets, TSMC is building on its production-ready ultra-low power N6e process by targeting the N4e process to enhance power efficiency for future edge AI applications.

Competition and U.S. investment

The symposium occurred amidst ongoing market speculation and governmental pressure regarding the relationship between TSMC and its U.S. competitor, Intel. TSMC’s chief, Dr. C.C. Wei, directly addressed recent reports suggesting a potential tie-up, including ideas pushed by Trump administration officials for TSMC to take a minority stake in Intel or help manage its fabrication plants. 

Dr. Wei stated that TSMC was “not engaged in any discussion with other companies regarding any joint venture, technology licensing or technology transfer and sharing.”

Attempting to transform Intel’s fabs to match TSMC’s standards would be a lengthy process, potentially taking many years and costing more than constructing new facilities. This proposal appeared to be part of the broader disruption introduced by the Trump administration’s trade and industrial policies.

Rendering of TSMC Fab 20 in Taiwan (Source: TSMC)

Despite denying specific tie-up reports, TSMC has significantly expanded its investment commitment in the United States following pressure from Trump officials. The company committed to more than doubling its U.S. investment to $165 billion, planning to build six fabs and two advanced packaging facilities. 

Competition between TSMC and Intel has also intensified as both companies work on integrating multiple chips into larger packages, a critical capability for high-end AI processors. While Intel is building its own contract manufacturing business and previously claimed it would surpass TSMC in making the fastest chips, analysts suggest the competitive landscape has shifted. 

Dan Hutcheson, vice chair at TechInsights, noted that the companies are “neck and neck,” and customer decisions might be driven by factors beyond the technological lead, such as customer service, pricing, and wafer allocation.

Financial performance and future outlook

TSMC recently reported robust financial results for the first quarter of 2025. Net profit surged by 60% compared to a year prior, reaching NT$361.56 billion ($11.13 billion). Revenues increased by 41.6% to NT$839.3 billion, aligning with the company’s earlier projections. This performance drove the gross margin up to 58.8%, near the upper end of management guidance.

However, TSMC warned that U.S. trade policy could further impact profit margins and harm demand. Dr. Wei acknowledged being “mindful of the potential impact of all the recent tariff announcements, especially on end demand.”

The company’s gross margins already affect the higher construction and operating costs associated with capacity expansion outside Taiwan. Chief Financial Officer Wendell Huang indicated that the projected annual margin dilution, previously forecast at 2% to 3%, could widen to 4% towards the end of five years.

The North America Technology Symposium served as TSMC’s flagship customer event of the year, drawing over 2,500 attendees. Beyond technology updates, the symposium provided an “Innovation Zone” for start-up customers to exhibit products and seek potential investors. The event also marked the beginning of a series of Technology Symposiums scheduled worldwide.